The present invention relates to a semiconductor integrated circuit device and a technique effective when used for a semiconductor integrated circuit device having, for example, a static RAM.
Japanese Unexamined Patent Publication No. 2001-344979 (Patent Document 1) discloses an invention for solving a problem such that leak current in an off state increases due to decrease in threshold voltage of a transistor as a device becomes finer by supplying negative voltage to a word line to which the gate of an accessed (selected) transistor is connected at the time of standby. Japanese Unexamined Patent Publication No. Hei 6(1994)-216346 (Patent Document 2) discloses an invention in which threshold voltage is set to be high in advance, at the time of operation, small voltage is supplied in a forward bias direction to a substrate so that the threshold voltage decreases, and operation is performed while assuring desired operating speed. At the time of standby, power source voltage and ground potential are supplied to the substrate to perform operation with the high threshold voltage, thereby reducing leak current.